Fabrication of atomic-scale dopant-in-silicon quantum processors

Fabrication of atomic-scale dopant-in-silicon for silicon quantum processors Abstract: Atomic-scale devices made from individual dopant atoms in silicon offer new ways to investigate physical phenomena and develop novel technologies. At Asentas Quantum Systems (AQS), we are developing a solid-state quantum processor architecture in which the valence electron of a single dopant atom serves as a spin qubit and the nuclear spin of the same atom is used as a quantum memory. I will introduce this architecture and describe the fabrication technology that underpins it. Our approach uses scanning tunneling microscopy hydrogen resist lithography (STM-HRL) to place individual dopant atoms deterministically with atomic-scale precision. Although STM-HRL is an established technique, the limited yield of single-atom fabrication has until recently been a major barrier scaling to large numbers of devices. I will show how we have overcome this limitation, achieving a single-atom yield approaching 100% for arsenic in silicon, providing a fabrication pathway to qubit scaling [1,2]. I will outline the full device fabrication process and present preliminary electrical measurements from arsenic-in-silicon devices fabricated using hydrogen resist lithography. Finally, I will set out AQS's vision for building a fault-tolerant quantum computer. Read More: Single-Atom Control of Arsenic Incorporation in Silicon for High-Yield Artificial Lattice Fabrication Atomic-Scale Patterning of Arsenic in Silicon by Scanning Tunneling Microscopy AGENDA: Thursday November 12, 2026 11:30 AM: Networking, Pizza & Drinks Noon -- 1 pm: Seminar Please register on Eventbrite before 9:30 AM on Thursday November 12, 2026 $4 IEEE members $6 non IEEE members (discounts for unemployed and students )