Meetup

Nov 4, 2026, 7:00 – 9:00 PM GMT+5:30

Special Programme on Advanced Research and Knowledge (SPARK -IX)

Date
Nov 4, 2026, 7:00 – 9:00 PM GMT+5:30

About this event

Event IEEE MTT-S GGV Student Branch Chapter, India, presents the Expert Talk Series - Special Programme on Advanced Research and Knowledge (SPARK-IX) on "Digital System Design Using Verilog." The session is designed to provide students with insights into digital system design using Verilog Hardware Description Language (HDL), bridging theoretical concepts with practical design and implementation techniques. Join us for an insightful technical session led by Dr. Sneha Sharma, Assistant Professor, Department of ECE, Dayananda Sagar University, Bangalore, India. Key Highlights Introduction to Verilog HDL: Understand the fundamentals of Verilog and its role in digital system design. Digital System Design: Explore the concepts and methodologies involved in designing digital circuits using Verilog. Simulation and Verification: Gain insights into simulating digital designs and verifying their functionality. FPGA Implementation: Understand how Verilog-based designs are implemented in FPGA platforms. Practical Design Approaches: Learn how theoretical digital electronics concepts translate into real-world hardware implementations. Interactive Learning: Participate in discussions and a question-and-answer session to enhance your understanding of Verilog and digital design. Event Details Date: Wednesday, 4th November 2026 Time: 07:00 PM - 08:00 PM IST Venue: Google Meet Event Type: Online