CMOS Scaling to Sub-nm Stacked CFETs

Moore's Law, six decades ago, set the course of complementary metal oxide semiconductor (CMOS) scaling, and its pace has essentially been dictated by dimensional reduction of device size. Then node-to-node performance improvements at fixed power, based on PPA (power-performance-area) efficiency - referred to as Dennard scaling started. The strong reduction in gate length and width led to an increase in off state leakage current and lower Ion/Ioff ratio. These short channel effects have driven technology to transition from planar MOSFETs to FinFETs, and recently, to gate-all-around (GAA) nanosheet (NS) transistors for high-performance computing applications. The scaling has led to larger effective widths per unit footprint area. Further promising structures are vertically stacked nanosheets and complementary field effect transistors (CFETs). In a CFET configuration, NMOS with Si channel and PMOS with SiGe channel devices are vertically stacked realized using multilayer epitaxial depositions and selective etchings. These advancements require innovations in device architecture, material & process engineering and design technology co-optimization (DTCO) when combined at standard cell level. These include, among others, advanced interconnect and middle-of-line schemes and the introduction of backside power delivery network (BSPDN). While the electrical and density improvements of CFET are undeniable, the architecture is accompanied by a new variety of challenges. Additionally, heat dissipation becomes a prominent issue. As more research is conducted on CFETs, more effective solutions will be implemented to address these challenges.